The present techniques relate to computer memory. More specifically, the techniques relate to the erasure of memory blocks in computer memory.
Computer memory may be organized in a hierarchy, from processor registers, over multiple cache levels, to external main memory. The highest or uppermost cache level is the one closest to the processor, and the lowest cache level is the one closest to the main memory. Access latency is lowest, and bandwidth is highest, for registers and upper cache levels. For example, a data word in core static random access memory (SRAM) may be accessed in 1 clock cycle. For the cache, accessing a data word may require two to tens of cycles, and for the main memory, up to hundreds of cycles.
On a memory level, the memory is partitioned into arrays, which make up random access memory (RAM) cores. The RAM cores are designed to have a relatively small physical area. The cores are combined into a memory array. Memory arrays are gathered together into units, and then connected into cache memory by multiplexers. At the array level, data is organized in words, with each word having a respective address. Each bit of each word is stored in a single cell. An SRAM cell may include 6 transistors, including two cross-coupled inverters (including 4 transistors) and two access transistors (or word line transistors). Write data is transmitted to the cells by bit lines. Read data is transmitted from the cell to the read-out circuit using either one of the two bit lines or using both bit lines. The number of cells on a bit line can be as any appropriate number, for example, from 16 to 1024 cells per bit line.